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CXD8302Q
PLL for CCD Cameras For the availability of this product, please contact the sales office.
Description The CXD8302Q has the functions needs to configure a PLL circuit with a timing generator and external sync signals for a CCD of 480K pixels (EIA, effective pixels) and 570K pixels (CCIR, effective pixels). Features * EIA and CCIR compatible * Compatible with component digital and composite digital recording format * Both SYNC and VD/HD signals can be used for external sync signals Absolute Maximum Ratings * Supply voltage VDD VSS - 0.3 to +7 V * Input voltage VI VSS - 0.3 to VDD+0.3 V * Storage temperature Tstg -40 to +125 C Recommended Operating Conditions * Supply voltage VDD 4.5 to 5.5 * Operating temperature Topr 0 to 70 Block Diagram
fH fV V reset 19 EXTfH
44 pin QFP (Plastic)
Applications CCD cameras Structure Silicon gate CMOS IC
V C
EXTSYNC EXTHD EXTVD
15 14 13
Separation of fH and fV 65 Clocks Delay V latch
MODE1 MODE2
26 31
Pulse Generation Circuit
Frequency Division EIA : 1/572 (1/568) CCIR: 1/576 (1/567) 2fH
H timing
20 41 42 43 44
INTfH HD VD SYNC BLK
Latch
EIA/CCIR
32
Frequency Division EIA : 1/525 CCIR: 1/625
V timing
CLKI
38
8 2 3 4 7 8 9 10 11
37
CLKO
INTfH phase setting
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94320A52-PP
CXD8302Q
Pin Configuration
EIA/CCIR
MODE2
MODE1
TEST6
VDD
TEST5
TEST4
Vss
NC
33 Vss 34 TEST7 35 NC 36 CLKO 37 CLKI 38 VDD 39 Vss 40 HD 41 VD 42 SYNC 43 BLK 44
32
NC
24
31
30
29
28
27
26
25
23 22 TEST3 21 TEST2 20 INTfH 19 EXTfH 18 TEST1 17 VDD 16 Vss 15 EXTSYNC 14 EXTHD 13 EXTVD 12 Vss
1
2
3
4
5
6
7
8
9
10
11
DLY0
Vss
DLY1
DLY3
DLY6
DLY2
DLY4
-2-
DLY5
DLY7
Vss
VDD
Vss
CXD8302Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol VSS DLY0 DLY1 DLY2 VDD VSS DLY3 DLY4 DLY5 DLY6 DLY7 VSS EXTVD EXTHD EXTSYNC VSS VDD TEST1 EXTfH INTfH TEST2 TEST3 VSS NC TEST4 MODE TEST5 VSS VDD TEST6 MODE2 EIA/CCIR NC VSS TEST7 NC CLKO I/O -- I I I -- -- I I I I I -- I I I -- -- O O O O O -- -- I I I -- -- I I I -- -- O -- O Inversed output of CLKI. -3- Test output (normally OPEN). Test input (normally High). (With pull-up resistor) Test input (normally High). High: SYNC sync mode, Low: VD/HD sync mode. Test input (normally Low). (With pull-up resistor) (With pull-up resistor) (With pull-down resistor) Test output (normally OPEN). External fH output. Internal fH output. Test output (normally OPEN). Test output (normally OPEN). External VD input. External HD input. External SYNC input. (With pull-up resistor) (With pull-up resistor) (With pull-up resistor) Pin 20 (INTfH) phase setting. Pin 20 (INTfH) phase setting. Pin 20 (INTfH) phase setting. Pin 20 (INTfH) phase setting. Pin 20 (INTfH) phase setting (MSB). (With pull-up resistor) (With pull-up resistor) (With pull-up resistor) (With pull-up resistor) (With pull-up resistor) Pin 20 (INTfH) phase setting. Pin 20 (INTfH) phase setting. Pin 20 (INTfH) phase setting. (With pull-up resistor) (With pull-up resistor) (With pull-up resistor) Description
High: Component digital mode, Low: Composite digital mode. (With pull-up resistor) High: EIA mode, Low: CCIR mode. (With pull-up resistor)
CXD8302Q
Pin No. 38 39 40 41 42 43 44
Symbol CLKI VDD VSS HD VD SYNC BLK
I/O I -- -- O O O O Horizontal sync signal output. Vertical sync signal output. Sync signal output. Blanking pulse output.
Description Clock input (from timing generator).
Electrical Characteristics 1) DC characteristics Item Input voltage High Low Symbol VIH VIL -10 VI = VDD VI = VSS IOH = -2mA IOL = 4mA 10 -8 2.4 1 35 -30 4.5 0.2 0.4 (VDD = 5V0.25V, Topr = 0 to 70C, VSS = 0V) Conditions Min. 0.7VDD 0.3VDD 10 120 -100 Typ. Max. Unit V V A A A V V
Input current 1 IIN1 (Input pins other than those below) Input current 2 (Input pins with pull-up resistor) Input current 3 (Input pins with pull-down resistor) Output voltage High Low IIN2 IIN3 VOH VOL
2) AC characteristics Vertical reset in VD/HD sync mode The phase of EXTVD should be input as shown in the diagram below against the first equivalent pulse during vertical blanking period. (Take care as the following conditions might not be satisfied depending on the phase setting of INTfH if the phases are locked when the falling phase shifts a lot between EXTfH and INTfH.)
SYNC
EXTVD
81 clocks
81 clocks
The EXTVD should fall at the timing shown with the slashes.
-4-
CXD8302Q
3) I/O pin capacitance (VDD = 5V0.25V, Topr = 0 to 70C, VSS = 0V) Item Input pin capacitance Symbol CIN Min. Typ. 2.0 4.0 Max. Unit pF pF
Output pin capacitance COUT Description of Operation
1) Operation overview * Functions as sync signal generator Each of fH (INTfH), VD, HD, SYNC, and BLK pulses is generated from clocks input by the timing generator. These pulses are generated by free running if external sync signals are not input. * External synchronization function (PLL) When the SYNC (EXTSYNC) or VD/HD (EXTVD/EXTHD) external sync signal is input, the vertical reset is compulsorily triggered on each of the fH (INTfH), VD, HD, SYNC, and BLK pulses, and fH (EXTfH) is simultaneously generated according to the external sync signal. Phase comparison is done externally between INTfH and EXTfH and a PLL circuit is configured, then the timing generator is synchronized with an external sync signal. 2) Mode setting Symbol EIA/CCIR Pin No. 32 L CCIR VD/HD sync mode: EXTVD/EXTHD is used as the external sync signal, and the EXTHD signal becomes EXTfH. Composite digital mode; Clock frequency input by timing generator EIA 17.897725MHz (1137.5fH = 5fsc) CCIR 17.734475MHz (1135 + 4/625fH = 4fsc) H EIA SYNC sync mode: EXTSYNC is used as the external sync signal, and the EXTfH is obtained by separating it from EXTSYNC Component digital mode: Clock frequency input by timing generator EIA 18MHz (1144fH) CCIR 18MHz (1152fH)
MODE1
26
MODE2
31
The phase relationship between external sync and EXTfH in each sync mode is shown below. * VD/HD sync mode The rise and fall timings of EXTHD signal are directly reflected on EXTfH.
EXTHD
EXTfH
* SYNC synchronous mode The fall timing of EXTSYNC is the fall timing EXTfH, but the rise timing of EXTfH is generated by counting the number of clocks input by the timing generator. Therefore, make sure to compare phases of fall timing of between EXTfH and INTfH for PLL configuration in the SYNC synchronous mode.
EXTSYNC (HSYNC)
EXTfH
42 clocks
42 clocks
-5-
CXD8302Q
3) INTfH phase setting In either VD/HD or SYNC sync mode, the INTfH phase should be adjusted in line with the phase variance of EXTfH, which forms the reference for phase comparison. The INTfH phase may be adjusted against VD, HD, SYNC and BLK pulses using DLY0 to DLY7, respectively. (The state of INTfH and EXTfH phases fixed by PLL leads to phase adjustment of VD, HD, SYNC, and BLK pulse against the external sync signal.) The INTfH is set to the phase being delayed (DELAY-64) clocks from that of HD. DELAY = 0 to 255: to be set in 8-bit binary with DLY7 as MSB. High: 1, low: 0.
(DELAY - 64) clocks
INTfH 128 clocks
HD 128 clocks
Example of System Configuration
Phase Comparator 36MHz (Component digital) 35.79545MHz (Composite digital, EIA) 35.56895MHz (Composite digital, CCIR)
LPF
VCO
EXTfH
INTfH
Electronic shutter serial data
External sync signal SYNC HD VD MODE1 15 14 13 26
fH Separation of fH and fv fV
19
20
33
XH1, 2 1/2 Frequency Division Pulse Generation Circuit 7 HD 41 VD 42 5 6 XRG XSUB XV1 to 4 XSG1, 2 SHP, SHD HCLP1, 2 VCLP PBLK CXD2422R (TG) To signal processing circuit To each driver
CLK 38 Frequency Division/ Pulse Generation Circuit
CXD8302Q
Note) 1. Either SYNC or VD/HD is used as the external sync signal.When SYNC is used (SYNC synchronous mode), fix MODE1 to High; when VD/HD is used (VD/HD synchronous mode), fix MODE1 to Low. 2. Be sure to do phase comparison of the falling edge of EXTfH and INTfH for SYNC synchronous mode.
-6-
Timing Chart (1) EIA vertical direction
Odd Field
HD 9H
VD
SYNC
BLK
20H
-7-
Even Field 9H 20H
HD
VD
SYNC
BLK
CXD8302Q
Timing Chart (1) EIA vertical direction
Odd Field
HD 9H
VD
SYNC
BLK
20H
-8-
Even Field 9H 20H CXD8302Q
HD
VD
SYNC
BLK
Timing Chart (2) CCIR vertical direction
Clock frequency 18MHz (Component digital mode) 17.897725MHz (Composite digital mode, EIA) 17.734475MHz (Composite digital mode, CCIR) -50 128 0 50 100 150 200
EIA
Number of clocks 0
HD 27 111
HSYNC 27 69
EQ 27
-57
VSYNC 196 (Component digital mode) 195 (Composite digital mode)
0
-9-
-50 0 50 100 128 150 0 29 113 29 71 29 0
H BLK
CCIR 200
Number of clocks
HD
HSYNC
EQ
-55
VSYNC 217 (Component digital mode) 214 (Composite digital mode) CXD8302Q
H BLK
CXD8302Q
Package Outline
Unit: mm
44PIN QFP (PLASTIC)
1.75 12.4 0.4 10.0 0.1 33 23 0.8 0.05 0.8 0.05
13
34
22
5
A
44
12
C
0.
1 0.3 0.1
6
11 0.8 0.15 0.15 0.05
- 0.15 0.15
MIN MAX
+ 2 5 - 5 DETAIL A
0.53
MAX
0.35 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.4g
SONY CODE EIAJ CODE JEDEC CODE
QFP-44P-L221 QFP044-P-1010-B
LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
- 10 -
11.24 0.2
10.76
0.58 0.2

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